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DCT: VLSI Implementation using Systolic Array - Ekta Agrawal

English
2014-03-01
€45.94 €57.42

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The discrete cosine transform (DCT) has been widely used in areas of speech and audio/video data compression. There are two traditional approaches to implementation of the DCT, implementations using butterfly structures or systolic arrays.Systolic array uses parallel pseudo-circular correlation structures as basic computational forms. The proposed algorithm can be mapped onto two linear systolic arrays with ... Full description

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Description

The discrete cosine transform (DCT) has been widely used in areas of speech and audio/video data compression. There are two traditional approaches to implementation of the DCT, implementations using butterfly structures or systolic arrays.Systolic array uses parallel pseudo-circular correlation structures as basic computational forms. The proposed algorithm can be mapped onto two linear systolic arrays with similar length and form that have a small number of I/O bandwidth that can be efficiently implemented into a VLSI chip. A highly efficient VLSI chip can be thus obtained that has good performances in the architectural topology, processing speed, hardware complexity and I/O costs and outperforms others especially in throughput. Here, we describe systolic array architectures for computation of the one-dimensional (1-D) Type-IV DCT. The proposed architectures employ simple PE¿s that require real multiplications and additions. They generate outputs sequentially with short computation time.

More Information

Author Ekta Agrawal
Publisher LAP LAMBERT Academic Publishing
Release year 2014
Cover type Softcover
EAN 9783846580547
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€45.94 €57.42