Static CMOS digital design has robust working performance, where logic levels are kept at the two extremes, either the ground voltage or supply voltage. However, the voltage excursion between the supply voltage and ground at all nodes causes excessive power dissipation. This condition also generates noise over the whole circuitry, which is not desirable especially in mixed signal designs. Current-mode digital design techniques can be a solution for this issue especially whenever the switching activity is high. In the first part, alternative current-mode arithmetic structures are built focusing on multi-valued circuits. Together with multi-valued logic implementations, signed-digit numbers and redundant number systems are also analyzed. In the second part, redundant arithmetic schemes for new generation reconfigurable systems are also analyzed. These techniques proposed here can be implemented efficiently by using recently introduced 6-input look-up table based field programmable gate array (FPGA) systems. A redundant double carry-save mode addition technique is proposed for the new generation FPGA devices.