Recent years have witnessed a huge increase in the power consumption of computing systems ranging from embedded systems to supercomputers. Power issues now drive major design decisions in businesses and large-scale enterprises and hence, the knowledge of how power concerns influence processor architecture is important for both researchers and business policy-makers. This book discusses basic concepts, algorithms and architectures for cache energy optimization in single-core and multi-core systems, multitasking, real-time and QoS systems. It presents dynamic reconfiguration based energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM. It also provides both qualitative and quantitative comparison with state-of-the-art cache energy saving techniques to stimulate the readers to take the frontiers beyond what has been presented here. This book will be useful for all those who are interested in power-aware computing and architecture design, be they students or researchers in computer architecture, chip designers, software engineers, technical marketing professionals or managers interested in low-power design.