Image watermarking in DCT domain has a high computational complexity especially for color and high resolution images, where usage of them has been significantly grown. To address this issue, a DCT watermarking algorithm for color images is selected and modified, to implement on FPGA and GPU, reducing execution time. For this, a hardware watermarking system is proposed to implement on FPGA and a data-parallel watermarking algorithm is proposed to implement on the GPU. To implement on FPGA, a new hardware architecture for inner product calculation is proposed and used in DCT and color space transformer modules. The architecture is based on integer computations and does not need to any ROM, floating point or any complicated circuit. Also, the architecture is two-dimensional pipelined, to operate at a high operating frequency. Furthermore, using the architecture, a 2D-DCT module is designed and used in the hardware watermarking system. Hardware architectures are synthesized on FPGA Virtex 7 and Spartan 3. Also, the GPU-based parallel watermarking algorithm is implemented on Geforce GT 540M and GTX 580.