Digital Circuits Using Subthreshold Leakage Power Reduction Techniques - M. Nakshatra,Kalagadda Bikshalu
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The numerous research efforts of low power VLSI design increased with the increasing demand of portable electronic appliances. Due to the advanced IC technology, the minimum feature size of VLSI circuitry continues to decrease. The VLSI chip manufacturers effectively utilizes the advantage of possible reduction in feature size by scaling (shrinking) the existing designs of VLSI chips which are capable in in ... Full description
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Description
The numerous research efforts of low power VLSI design increased with the increasing demand of portable electronic appliances. Due to the advanced IC technology, the minimum feature size of VLSI circuitry continues to decrease. The VLSI chip manufacturers effectively utilizes the advantage of possible reduction in feature size by scaling (shrinking) the existing designs of VLSI chips which are capable in increasing speed of the circuit. The reduction in geometry of transistor and as the number of transistors on a single chip grows exponentially; the power management for VLSI design has become vital.The sub threshold leakage is the main component of leakage power in VLSI circuits. This leakage is to be reduced so that power is handled in a better way. The techniques like CMOS, stack, sleep and sleepy keeper are used to control sub threshold leakage. These effective low power digital circuit design techniques reduces the overall power dissipation.The characteristics of digital circuit like inverter, nand, nor, exclusive-or, half adder and half subtractor are analyzed and compared in different technologies like 45nm, 120nm, 180nm.
More Information
| Author | M. Nakshatra, Kalagadda Bikshalu |
|---|---|
| Publisher | LAP LAMBERT Academic Publishing |
| Release year | 2016 |
| Cover type | Softcover |
| EAN | 9783659913969 |