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Generating Code from Abstract VHDL Models: Basics, Semantics, Algorithms - Mohamed Abdel Maksoud

English
2008-06-01
€73.18 €91.48

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Static methods are very successful in deriving crucial properties (e.g.timing behaviour) of safety critical systems. Some information in the analysed program are not available either because they cannot be determined statically or because they were intentionally sacrificed (i.e.abstracted) to make program analysis tractable. These abstractions make program simulation nondeterministic. This book describes th ... Full description

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Description

Static methods are very successful in deriving crucial properties (e.g.timing behaviour) of safety critical systems. Some information in the analysed program are not available either because they cannot be determined statically or because they were intentionally sacrificed (i.e.abstracted) to make program analysis tractable. These abstractions make program simulation nondeterministic. This book describes the algorithms and semantics developed and used in building an abstraction-aware compiler that derives/generates pipeline analysis from an abstracted VHDL specification of the target microprocessor. This analysis is used in a commercial tool frame for deriving upper bound over execution time of critical tasks.This book is useful for computer scientists and engineers concerned with computing timing analyses based on VHDL specification of the target hardware.

More Information

Author Mohamed Abdel Maksoud
Publisher VDM Verlag
Release year 2008
Cover type Softcover
EAN 9783639024685
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€73.18 €91.48